1. Field of the Invention
The present invention relates to metal interconnect structures. More particularly, the present invention relates to copper interconnects with metal alloy capping layers having reduced electrical resistivity impact from alloy elements in the copper interconnect structure.
2. Description of the Related Art
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
In semiconductor interconnect structures, electromigration (EM) has been identified as one metal failure mechanism. EM is one of the worst reliability concerns for very large scale integrated (VLSI) circuits and manufacturing since the 1960's. The problem not only needs to be overcome during the process development period in order to qualify the process, but it also persists through the lifetime of the chip. Voids are created inside the metal conductors of an interconnect structure due to metal ion movement caused by the high density of current flow.
Although the fast diffusion path in metal interconnects varies depending on the overall integration scheme and materials used for chip fabrication, it has been observed that metal atoms, such as Cu atoms, transported along the metal/post planarized dielectric cap interface play an important role on the EM lifetime projection. The EM initial voids first nucleate at the metal/dielectric cap interface and then grow in the direction of the bottom of the interconnect, which eventually results in a circuit opening.
Copper interconnects containing a metal cap have been approved as a preferred structure to resist electromigration. While various alternate metal capping approaches have been proposed to reduce electromigration-induced copper transport and void growth, virtually all involve a tradeoff between improvement and copper resistivity increase. Additional liabilities may include undesirable line-to-line leakages and capacitance increases. Cobalt-tungsten-phosphorus capping processes have been recently evaluated and demonstrated as a promising process to enhance electromigration resistance. However, this electroless plating approach adds processing steps, for example, pre- and post-cleans, and increases wafer cost. Copper-manganese alloy seeding processes have also been recently evaluated and demonstrated as a promising process to enhance electromigration resistance. However, “residual” manganese within the copper interconnect increases the electrical resistivity.
In view of the above, there is a need for providing an interconnect structure which avoids a circuit opening caused by EM failure as well as electrical shorts between adjacent interconnect structures.